1. Field of the Invention
This invention generally relates to a buffer circuit. This invention particularly relates to a buffer circuit which generates a rail-to-rail output signal in response to an input dc voltage.
2. Description of the Related Art
Japanese published unexamined patent application 61-295709 discloses an operational amplifier having a first differential amplifier portion, a second differential amplifier portion, a level shift means, and a final amplifier portion. In the operational amplifier of Japanese application 61-295709, the first differential amplifier portion uses an N-channel MOS FET as an input transistor while the second differential amplifier portion uses a P-channel MOS FET as an input transistor. The level shift means receives the output signal of one of the first and second differential amplifier portions, and shifts the level of the received signal. The resultant output signal of the level shift means and the output signal of the other of the first and second differential amplifier portions are fed to the final amplifier portion.
Japanese published unexamined patent application 5-129848 discloses an offset voltage compensating circuit for a differential amplifier. The circuit of Japanese application 5-129848 includes a short-circuiting switch SW1 to set input terminals of a differential amplifier at the same voltage, capacitors C1 and C2 connected to a node to change the output voltage of the differential amplifier, and charge/discharge switches SW3-SW6 to connect the capacitors C1 and C2 to a charging source or a discharging source. Also, the circuit of Japanese application 5-129848 includes a comparator and a switch control circuit. The comparator operates to compare an output voltage from the differential amplifier with a prescribed reference voltage. The switch control circuit operates the short-circuiting switch SW1 when receiving a compensation starting signal. The switch control circuit operates the charge/discharge switches SW3-SW6 in response to an output signal of the comparator so that the output voltage of the differential amplifier can be coincident with the prescribed reference voltage.
Japanese published unexamined patent application 8-204468 discloses an operational amplifier including first and second differential amplifier circuits subjected to a common input voltage. In the operational amplifier of Japanese application 8-204468, the first differential amplifier circuit can operate when the input voltage is higher than a first voltage range within a fixed voltage range measured from a lower-side power supply voltage. The second differential amplifier circuit can operate when the input voltage is lower than a second voltage range within a fixed voltage range measured from a higher-side power supply voltage. A top of the first differential amplifier circuit has an N-channel transistor while a top of the second differential amplifier circuit has a P-channel transistor. In the operational amplifier of Japanese application 8-204468, the first differential amplifier circuit is provided with first offset trimmer circuits for adjusting the offset thereof when the input voltage is in the second voltage range. The second differential amplifier circuit is provided with second offset trimmer circuits for adjusting the offset thereof when the input voltage is in the first voltage range.
In general, a buffer circuit using an operational amplifier tends to have a problem of an offset voltage.